Device Family: Intel® Stratix® 10

Type: Answers, Errata

Area: Intellectual Property


Last Modified: October 12, 2018
Version Found: v17.1 Update 1
Version Fixed: v18.1
Bug ID: FB: 521959, 516942;

Why does the Intel® Stratix® 10 Low Latency 40-Gbps Ethernet IP Core fail to detect and flag oversized packets when the frame length is greater than or equal to 0x10000?

Description

Due to a code limitation, the frame length counter in the Intel® Stratix® 10 Low Latency 40-Gbps Ethernet IP Core will overflow when the frame length is greater than or equal to 0x10000h bytes. The Intel® Stratix® 10 Low Latency 40-Gbps Ethernet IP will fail to detect that the packet length is greater than the length defined in the MAX_TX_SIZE_CONFIG/MAX_RX_SIZE_CONFIG registers, and as a consequence the oversize frame counter registers will not be incremented to indicate the reception of an oversized frame.

Workaround/Fix

To work around this problem use frame lengths less than 0x10000h bytes.

This problem has been fixed starting in the Intel® Quartus® Prime software version 18.1.