Article ID: 000083198 Content Type: Troubleshooting Last Reviewed: 05/14/2018

Why are the Ax, Ay, Az, and Chainin ports missing from the block symbol and HDL instantiation template of the Intel® Stratix® 10 Native Floating Point DSP IP?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Native Floating Point DSP Intel® Stratix® 10 FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with the Intel® Stratix® 10 Native Floating Point DSP IP in Intel® Quartus® Prime Pro software version 17.1, you may observe that the Ax, Ay, Az, and Chainin ports are missing from the block symbol and HDL instantiation template if the IP is configured with Vector Mode 2. 

    Resolution

    This problem has been fixed starting in v18.0 of the Intel Quartus Prime Pro software.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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