Device Family: Intel® Stratix® 10

Type: Answers

Area: DSP, Intellectual Property


Last Modified: May 14, 2018
Version Found: v17.1
Version Fixed: v18.0
Bug ID: FB: 541680;
IP: Stratix 10 Native Floating Point DSP

Why are the Ax, Ay, Az, and Chainin ports missing from the block symbol and HDL instantiation template of the Intel® Stratix® 10 Native Floating Point DSP IP?

Description

Due to a problem with the Intel® Stratix® 10 Native Floating Point DSP IP in Intel® Quartus® Prime Pro software version 17.1, you may observe that the Ax, Ay, Az, and Chainin ports are missing from the block symbol and HDL instantiation template if the IP is configured with Vector Mode 2. 

Workaround/Fix

This problem has been fixed starting in v18.0 of the Intel Quartus Prime Pro software.