Device Family: Intel® Arria® 10, Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX

Type: Answers, Errata

Area: Intellectual Property


Last Modified: August 14, 2018
Version Found: v18.0
Bug ID: FB: 545522;

The Intel® Arria® 10 PCIe* Hard IP Avalon®-MM TXS bridge does not support completion without data after sending a memory read request when the RootPort is in any power management D-state.

Description

According to PCIe spec, when a RootPort sends a memory request during power management D-state, the EndPoint should return a completion without data. Whilst the Intel® Arria® 10 PCIe* Hard IP is able to receive the completion without data, the Avalon®-MM TXS bridge always expects completion with data. The Avalon-MM TXS bridge will drop any completion without data after a memory read request is sent from the Avalon-MM TXS interface.

When user application uses the Intel® Arria® 10 Avalon®-MM Interface for PCIe* in Root Port mode,  the connected endpoint will always receive completion with data after the endpoint sends memory read request.

According to PCIe* spec, when a RootPort is in any power management D-state, it should send completion without data after receiving a memory read request. the Intel® Arria® 10 Avalon®-MM Interface for PCIe* in Root Port mode violates this rule.

Workaround/Fix

No workaround for this problem exists. The user application and software should be aware of the limitation and ensure that this scenario doesn't happen.

When using the Intel® Arria® 10 Avalon®-MM Interface for PCIe* in Root Port mode, be aware that the endpoint will always receive completion with data from an Intel® Arria® 10 Avalon®-MM Interface for PCIe* in Root Port mode.

This problem will not be fixed in a future release of the Intel® Quartus® Prime software as the Intel® Arria® 10 Hard IP has limited support for the power management D-state.