According to PCIe spec, when a RootPort sends a memory request during power management D-state, the EndPoint should return a completion without data. Whilst the Intel® Arria® 10 PCIe* Hard IP is able to receive the completion without data, the Avalon®-MM TXS bridge always expects completion with data. The Avalon-MM TXS bridge will drop any completion without data after a memory read request is sent from the Avalon-MM TXS interface.
When user application uses the Intel® Arria® 10 Avalon®-MM Interface for PCIe* in Root Port mode, the connected endpoint will always receive completion with data after the endpoint sends memory read request.
According to PCIe* spec, when a RootPort is in any power management D-state, it should send completion without data after receiving a memory read request. the Intel® Arria® 10 Avalon®-MM Interface for PCIe* in Root Port mode violates this rule.