Device Family: Intel® Stratix® 10

Type: Answers, Errata

Area: Intellectual Property

Last Modified: November 29, 2017
Version Found: v17.1
Bug ID: FB: 508093;
IP: Avalon-ST Stratix 10 Hard IP for PCI Express

Why does the lane_act bus show incorrect link widths for my Stratix 10 H-tile Hard IP for PCI Express?


Due to a problem with the Hard IP for PCI Express* on the Intel® Stratix® 10 H-Tile Production devices, you will see incorrect encoding of the lane_act bus as shown in the following table:

Actual Link Width lane_act value Link Width according to the user guide encoding
x1 5'b1 0000 x16
x2 5'b0 0001 x1
x4 5'b0 0010 x2
x8 5'b0 0100 x4
x16 5'b0 1000 x8


To work around this problem, which only affects H-tile production devices, interpret lane_act using the first two columns in table above.

This problem will be fixed by soft logic in a future Intel® Quartus® Prime software release.