Device Family: Intel® Stratix® 10

Type: Answers, Errata

Area: Intellectual Property

Last Modified: January 23, 2018
Version Found: v17.0
Bug ID: FB: 502069, 508093;
IP: Avalon-MM Stratix 10 Hard IP for PCI Express, Avalon-ST Stratix 10 Hard IP for PCI Express

Why does the Intel® Stratix® 10 Hard IP for PCIe* report incorrect link widths?


Due to an encoding problem with the link acknowledge logic in Intel® Stratix® 10 H-Tile ES2 devices, link widths will be incorrectly acknowledged as shown below:

Actual Link Width Link Acknowledge
x1 x16
x2 x1
x4 x2
x8 x4
x16 x8


This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.