When using the Intel® Stratix® 10 L- and H-Tile Transceiver PHY IP in bonding mode, use the tx_coreclk from the master channel as the source clock for all of the other channels in the bonded interface. If this guideline is not met, you will see timing violations for a clock transfer from one tx_outclock domain to another.
Device Family: Intel® Stratix® 10
Intel Software: Quartus Prime Pro
Last Modified: December 12, 2018
Version Found: v18.1
Bug ID: FB: 1408300344;