Device Family: Intel® Stratix® 10

Type: Answers, KDB Area

Area: HSIO


Last Modified: January 26, 2018
Version Found: v17.1 Update 1
Bug ID: FB: 525385;

Info: mypll.xcvr_atx_pll_s10_htile_0: The current value "GX clock output buffer" for parameter "Primary PLL clock output buffer" (primary_pll_buffer) is invalid.

Description

You may see the following message in the Stratix® 10 L-Tile or H-Tile ATX PLL IP Paramater Editor message pane when configuring your PLL for dynamic reconfiguration between GX and GXT modes using the configuration profiles feature.

Info: mypll.xcvr_atx_pll_s10_htile_0: The current value "GX clock output buffer" for parameter "Primary PLL clock output buffer" (primary_pll_buffer) is invalid. Possible valid values are: "GXT clock output buffer".  

Workaround/Fix

The message indicates that the GX clock output buffer mode is invalid, but the message is green in colour indicating that it is valid.

The message refers to the output buffer mode for the inactive configuration, and can be safely ignored.