You may see the following message in the Stratix® 10 L-Tile or H-Tile ATX PLL IP Paramater Editor message pane when configuring your PLL for dynamic reconfiguration between GX and GXT modes using the configuration profiles feature.
Info: mypll.xcvr_atx_pll_s10_htile_0: The current value "GX clock output buffer" for parameter "Primary PLL clock output buffer" (primary_pll_buffer) is invalid. Possible valid values are: "GXT clock output buffer".