Device Family: Arria® II, Arria® V, Cyclone® V, Stratix® III, Stratix® IV, Stratix® V

Intel Software: Quartus Prime Standard

Type: How-To

Area: EMIF

Version Found: v16.0
Bug ID: 1507279790
IP: memory-interfaces-with-uniphy

How can the mem_clk delay steps of the Intel® UniPHY IP controllers be changed by the ECO flow?


For debug investigative purposes, it is sometimes useful to change the I/O delay steps of external memory signals (for example, mem_clk delay steps) of the Intel® UniPHY IP controllers using the engineering change order (ECO) flow .

For example, below are the steps to change the D5 delay.

1. Open Pin Planner, select the mem_clk pin that you want to delay and right-click and choose Locate Node > Locate in Resource Property Viewer.

2. In Resource Property Viewer, select all mem_clk pin.

3. Select pad on Properties windows, locate D5 delay chain, and select new value.

4. Once you have selected D5 value, go to Resource Property Viewer and select Check and Save All Netlist Changes.

5. Run the Assembler to regenerate the new programming .sof file.