Device Family: Intel® Arria® 10

Type: Answers

Area: EMIF


Version Found: v16.0
Bug ID: FB: 546929;
IP: Altera PHYLite for Parallel Interfaces, Arria 10 External Memory Interfaces

Why does the EMIF calibration hang when both an Intel® Arria® 10 External Memory Interfaces IP and an Intel Arria 10 PHYLite IP are placed in the same I/O column?

Description

Both the local_cal_fail signal and the local_cal_success signal may not assert high after EMIF calibration when both an Intel® Arria® 10 EMIF IP and an Intel Arria 10 PHYLite IP with dynamic reconfiguration enabled are placed in the same I/O column.

Workaround/Fix

This problem is scheduled to be fixed in a future release of the Intel Quartus® Prime software.