Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: EMIF


Last Modified: November 01, 2018
Version Found: v17.1
Bug ID: FB: 503635 605451;
IP: Stratix 10 External Memory Interfaces

Error(19433): Transfer between periphery and DSP or RAM <signal_path> will make timing transfer impossible.

Description

You may see a similar error in synthesis when you connect the Avalon-MM Clock Crossing Bridge to the Avalon or MMR interface of the Intel® Stratix® 10 FPGA EMIF IP in the Intel® Quartus® Prime Platform Designer version 17.1 or earlier.  

Error(19433): Transfer between periphery and DSP or RAM <signal_path1> through logic cell <signal_path2> will make timing transfer impossible.

 

Workaround/Fix

This problem is fixed in the Intel® Quartus® Prime Software version 17.1.1 or later.