Device Family: Intel® Arria® 10

Type: Answers

Area: EMIF


Last Modified: November 14, 2017
Version Found: v16.0
Bug ID: FB: 480925;
IP: Arria 10 External Memory Interfaces

What is the minimum pulse width required for the Arria 10 EMIF IP global_reset_n signal ?

Description

The minimum reset pulse width requirement is 100ns.