Device Family: Intel® Stratix® 10 SX, Intel® Stratix® 10 TX

Intel Software: SoC EDS

Type: Answers, Errata

Area: Embedded, SoC FPGA Linux


Last Modified: May 26, 2020
Version Found: v18.1 Update 2
Bug ID: 1409342244

Why does FPGA configuration fail from Linux / u-boot fail on Intel® Stratix® 10 SX devices when I use phase 2 bitstreams generated from different Quartus Projects?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition software versions 20.1 and earlier,  FPGA configuration from Linux / u-boot as part of an HPS First boot flow may fail for designs targeting Intel Stratix® 10 SX devices if Phase 1 and Phase 2 bitstreams are generated from different Intel® Quartus® Prime Pro Projects.

The following errors may be seen:

Stratix10 SoC FPGA manager soc:firmware:svc:fpga-mgr: ERROR - giving up - SVC_STATUS_RECONFIG_ERROR

Stratix10 SoC FPGA manager soc:firmware:svc:fpga-mgr: s10_ops_write not all buffers were freed

fpga_manager fpga0: Error while writing image data to FPGA

Workaround/Fix

To resolve this problem in the Intel® Quartus® Prime Pro Edition software version 19.1: 

 

To resolve this problem in the Intel® Quartus® Prime Pro Edition software versions 19.2, 19.3 and 19.4

  • The INI setting documented in  19.1-0.13 readme must be in place

 

To resolve this problem in the Intel® Quartus® Prime Pro Edition software versions 20.1 and later

  • The following global assignment must be added to the  <project name>.qsf  settings file
    • set_global_assignment -name INI_VARS "asm_constant_hpsio_hash = on"

This problem is scheduled to be resolved in a future release of the Intel® Quartus® Prime Pro software.