Due to a problem in the Intel® Quartus® Prime Pro Edition software versions 20.1 and earlier, FPGA configuration from Linux / u-boot as part of an HPS First boot flow may fail for designs targeting Intel Stratix® 10 SX devices if Phase 1 and Phase 2 bitstreams are generated from different Intel® Quartus® Prime Pro Projects.
The following errors may be seen:
Stratix10 SoC FPGA manager soc:firmware:svc:fpga-mgr: ERROR - giving up - SVC_STATUS_RECONFIG_ERROR
Stratix10 SoC FPGA manager soc:firmware:svc:fpga-mgr: s10_ops_write not all buffers were freed
fpga_manager fpga0: Error while writing image data to FPGA