Article ID: 000073919 Content Type: Product Information & Documentation Last Reviewed: 05/20/2021

How many Clock Control Intel FPGA IP for clock input muxing is available in an Intel® Stratix® 10 device?

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    Description

    There is no definite maximum number of the Clock Control Intel® FPGA IP for clock input muxing in an Intel® Stratix® 10 device.
    Unlike the Clock Control Block (ALTCLKCRTL) IP in previous Intel® FPGA devices, the Clock Control Intel® FPGA IP consists of logic element when the IP is used for clock input muxing without clock gating or output division option. So the maximum number depends on device utilization and design complexity.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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