Due to the nature of the DCFIFO IP in Intel® Stratix® 10 device, wrong data may be observed at the show-ahead output or the first read operation after resetting by aclr. This symptom is only observed when a racing condition occurs between aclr deassertion and rdclk rising edge.
Device Family: Intel® Stratix® 10
Intel Software: Quartus Prime Pro
Version Found: v19.3
Bug ID: 14011835528