Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Component


Version Found: v19.3
Bug ID: 14011835528

Why does a DCFIFO IP output wrong data at the show-ahead output or the first read operation after resetting by aclr in Intel® Stratix® 10 device?

Description

Due to the nature of the DCFIFO IP in Intel® Stratix® 10 device, wrong data may be observed at the show-ahead output or the first read operation after resetting by aclr.  This symptom is only observed when a racing condition occurs between aclr deassertion and rdclk rising edge.

Workaround/Fix

Use Add circuit to synchronize 'aclr' input with 'rdclk' option from the FIFO parameter editor, or setting the READ_ACLR_SYNCH parameter to ON

This will be described in future release of Intel® Stratix® 10 Embedded Memory User Guide.