Device Family: Intel® Stratix® 10 MX, Intel® Stratix® 10 TX

Intel Software: Quartus Prime Pro

Type: Answers

Area: Component


Last Modified: November 03, 2020
Version Found: v20.2
Version Fixed: v20.3
Bug ID: 14011202552
IP: On-Chip Memory (RAM or ROM)

Why do the channels of the eSRAM Intel® Stratix® 10 FPGA IP fail to return correct data?

Description

When the eSRAM Intel® Stratix® 10 FPGA IP is included in your design, you might see an incorrect data or all "zero" data in some channels.

Workaround/Fix

To work around this problem, include the Reset Release Intel® FPGA IP and connect the nINIT_DONE output signal from the Reset Release Intel FPGA IP to the input signal c<channel_number>_sd_n_0 of the eSRAM Intel Stratix® 10 FPGA IP.

 

This information is included in the Intel Stratix 10 Embedded Memory User  Guide.