Device Family: Intel® Stratix® 10 MX, Intel® Stratix® 10 TX

Intel Software: Quartus Prime Pro

Type: Answers

Area: Component

Last Modified: October 07, 2020
Version Found: v19.3
Bug ID: 2209854465

Why do I read all "zero" data from eSRAM Intel® Stratix® 10 FPGA IP intermittently ?


When you tie the c<channel_number>_sd_n_0 port to a logic '1' or '0' in RTL you may see "zero" read data from eSRAM Intel® Stratix® 10 FPGA IP.


To work around this connect signals from user logic to the c_<channel_number>sd_n_0 ports. 

This issue is scheduled to be fixed in future release of the Intel Quartus® Prime Pro software.