Device Family: Intel® Stratix® 10

Type: Answers

Area: Component


Last Modified: Mon Mar 11 2019 21:11:00 GMT-0700
Bug ID: 1507098925

What is the maximum supported frequency of the input clock in the Mailbox Client Intel® Stratix® 10 FPGA IP Core?

Description

The maximum supported frequency of the input clock in the Mailbox Client Intel® Stratix® 10 FPGA IP Core is 250 MHz.

Please note that the actual allowable maximum frequency depends on user design.

Workaround/Fix