Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime

Type: Answers

Area: Component



How do I get package RLC parasitic value per pin for Intel® Stratix® 10 devices?

Description

The RLC parasitic value for each pin of Intel® Stratix® 10 devices is not included in the stratix10 rlc.xls file which can be downloaded from  IBIS Models for Intel® Devices

You need to generate the IBIS model first based on your target device and enable RLC option when generating the model.

Workaround/Fix

You can generate an IBIS model file with Intel Quartus Prime® Edition software based on your target device and  pin assignment and get the RLC value by following these steps.

Go to Settings--> EDA Tool Settings--> Board level signal integrity analysis--> format: IBIS and enable model selector and extend model selector.

Then re-compile the design after applying these settings.

The RLC value for each pin used in your project will be included in the generated *.ibs file as shown in the example below. The RLC values are listed in the right column.


[Pin] signal_name                                     model_name                             R_pin L_pin C_pin
|

AA1 tx_datak(2)~pad                               18_rtin_lv                                  1075.3m 6.327nH 2.200pF
AA2 tx_parallel_data(2)~pad                 18_rtin_lv                                   976.1m 5.828nH 2.147pF
AA4 tx_parallel_data(15)~pad               18_rtin_lv                                  831.8m 4.855nH 1.948pF
AA5 VCCIO3A POWER
AA8 tx_parallel_data(20)~pad               18_rtin_lv                                  969.1m 5.378nH 2.470pF
AA9 tx_datak(1)~pad                               18_rtin_lv                                  993.4m 5.810nH 2.499pF
AB1 tx_parallel_data(24)~pad               18_rtin_lv                                  1074.7m 6.252nH 2.237pF