Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Component


Last Modified: September 28, 2018
Bug ID: FB: 590454;
IP: Altera S10 Mailbox Client

How can the data stored in the read data FIFO in Stratix® 10 Serial Flash Mailbox Client Intel® FPGA IP Core be read with a JTAG Master as host?

Description

The read data FIFO can be accessed through the “rd_mem” bus in Stratix® 10 Serial Flash Mailbox Client Intel® FPGA IP Core. To read data stored in the read data FIFO, you need to read data from the “rd_mem” bus. Refer to the IP rd_mem’s base and end address  in the Intel® Quartus® Prime Platform Designer for the start address and list of addresses that you can read into.

For more details about the read operation flow, refer to Stratix® 10 Serial Flash Mailbox Client Intel® FPGA IP Core User Guide.

 

Workaround/Fix