Device Family: Intel® Stratix® 10 GX, Intel® Stratix® 10 SX

Type: Answers

Area: Component


Last Modified: February 02, 2018
Bug ID: FB: 505228;
IP: Altera IOPLL

How can I achieve the IOPLL jitter performance as specified in the Intel® Stratix® 10 device datasheet?

Description

To achieve the Intel® Stratix® 10 IOPLL jitter performance as specified in the Intel Stratix 10 Device Datasheet, limit the number of unterminated simultaneously switching output (SSO) pins within an IO bank to the number specified in the table below, for each current strength

SSO Pin Current Strength (mA)

Maximum Number of SSO Pins

Jitter Increment per SSO Pin (ps/pin)

16

17

8

12

21

7

10

27

6

8

36

4

If your application requires more unterminated pins to toggle simultaneously, then the PLL output jitter specification will be impacted by the amount specified in the table. External memory interface specifications are not impacted as the effect of additional jitter is accounted for in the maximum data rates supported by the Stratix 10 devices.

This guideline is applicable to following devices:

  • Stratix 10 GX ES3 and production devices
  • Stratix 10 SX ES1, ES2 and production devices

Workaround/Fix