Device Family: Arria® II, Arria® GX, Intel® Cyclone®, Intel® Cyclone® 10 LP, Cyclone® II, Cyclone® III, Cyclone® IV, Intel® MAX® 10, Intel® Stratix®, Stratix® II, Stratix® III, Stratix® IV

Intel Software: Quartus Prime Standard

Type: Answers

Area: Component


Last Modified: November 23, 2018
Version Found: v18.1
Bug ID: FB: 411002/ 2205746033;

Fatal: (vsim-3817) Port "configupdate" of entity "system_altpll_0" is not in the component being instantiated.

Description

Due to a problem in the Intel® Quartus® Prime Standard Edition software version 18.1 and earlier, you may see Fatal Error message mentioned above when simulating VHDL based simulation model of ALTPLL Intel FPGA IP.

Workaround/Fix

To work around this problem, update simulation script to use the IP top level wrapper file from <ip name>/synthesis/ directory instead of <ip name>/simulation/ directory.