Intel provides extensive support for the 10 Gbps Ethernet (10GbE) media access control (MAC) Megacore® function to help you quickly and easily develop and debug 10GbE applications such as line cards, network interface cards (NICs), and switches operating at 10 gigabits per second (Gbps).
- 10 Gbps Ethernet MAC MegaCore Function User Guide (PDF)
- Intel FPGA IP Release Notes (PDF)
- Transceiver PHY IP Core User Guide (PDF)
- Archive of intellectual property release notes
AN 638-10-Gbps Ethernet MAC and XAUI PHY Interoperability Hardware Demonstration Reference Design
Note: For Stratix V device design compiled prior to ACDS 13.0, if you regenerate ETH10G.qsys file and encounter fitter error due to bonded channel placement, please follow the instruction below before you compile the design:
- Search for the file altera_xcvr_xaui in Qsys folder ./ETH10G_TOP/synthesis/submodules
- Search for the module sv_xcvr_xaui in the above file
- Edit the bonded mode parameter:
- Before: xN
- After : fb_compensation
The Knowledge Database provides support solutions, answers frequently-asked questions, and information about known issues regarding the 10GbE reference design.
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The following development kits are available for the 10GbE reference design: