This example demonstrates how to implement a multiple-channel variable-rate decimation filter in the Intel® DSP Builder Advanced Blockset. For many medical imaging systems including ultrasound and magnetic resonance imaging (MRI) a reconfigurable decimation filter is needed to reduce the echo data sample rate. The input data has a fixed sample rate; however the integer decimation rate needs to be changed real-time. Furthermore, the total filter length grows linearly with the decimation rate. Similar requirements may apply in wireless communications applications and other systems. The polyphase structure is highly optimized for this type of applications, because the multiplier count is fixed at compile time and does not grow with rate increase. The key features of this design are the variable-length delay taps and efficient filter coefficient storage.
Features
This design example has the following key features:
- Support for arbitrary integer decimation rates, including the cases without sample rate change
- Support for an arbitrary number of channels, arbitrary clock rates, and input sample rates, as long as the clock rate is high enough to process all the channels in a single datapath, or in other words, no hardware duplication
- Support for run-time reconfiguration of decimation rates
- Use of two memory banks for filter coefficient storage instead of pre-storing coefficients for all rates in the memory. This feature enables one memory bank to be updated while the design is reading coefficients from the other bank
- Real-time control of scaling in the finite impulse response (FIR) datapath
Functional Description
The design uses a direct-form polyphase decimation filter structure and is shown in Figure 1. The address controller generates the reading address of the coefficient memory, a bank selector, and the writing address of the variable delay taps. The coefficients are stored in on-chip RAM blocks. The variable delay taps are also implemented in dual-port memories, and its pointer is controlled by the current decimation rate. A fixed number of multipliers is used.