This example demonstrates how to implement a multiple-channel variable-rate decimation filter in the Altera® DSP Builder Advanced Blockset. For many medical imaging systems including ultrasound and magnetic resonance imaging (MRI) a reconfigurable decimation filter is needed to reduce the echo data sample rate. The input data has a fixed sample rate; however the integer decimation rate needs to be changed real-time. Furthermore, the total filter length grows linearly with the decimation rate. Similar requirements may apply in wireless communications applications and other systems. The polyphase structure is highly optimized for this type of applications, because the multiplier count is fixed at compile time and does not grow with rate increase. The key features of this design are the variable-length delay taps and efficient filter coefficient storage.
Features
This design example has the following key features:
Support for arbitrary integer decimation rates, including the cases without sample rate change
Support for an arbitrary number of channels, arbitrary clock rates, and input sample rates, as long as the clock rate is high enough to process all the channels in a single datapath, or in other words, no hardware duplication
Support for run-time reconfiguration of decimation rates
Use of two memory banks for filter coefficient storage instead of pre-storing coefficients for all rates in the memory. This feature enables one memory bank to be updated while the design is reading coefficients from the other bank
Real-time control of scaling in the finite impulse response (FIR) datapath
Functional Description
The design uses a direct-form polyphase decimation filter structure and is shown in Figure 1. The address controller generates the reading address of the coefficient memory, a bank selector, and the writing address of the variable delay taps. The coefficients are stored in on-chip RAM blocks. The variable delay taps are also implemented in dual-port memories, and its pointer is controlled by the current decimation rate. A fixed number of multipliers is used.
Figure 1. Block Diagram of the Variable Rate Decimator
The variable tap delay blocks in this example have a run-time reconfigurable depth. Therefore, they are implemented as elastic memories using on-chip RAM blocks. Each delay tap is allocated based on the worst case. The actual number of delays through a delay tap block is based on the current decimation rate. A single pointer or address signal is used for both the reading and writing operations into the delay tap. Therefore you will read and write into the same memory location. The two-port RAM is configured to read out old memory contents, thus realizing a delay of a certain number of cycles.
This design uses only two memory banks, with one being updated while the other one is being read from. A processor interface is needed to realize coefficient reload at run time.
In the setup script for this design, we defined clock rate, decimation rate, filter length, multiplier engine etc. Bit-width management is also scripted for parameterization. The key parameters and their definitions are listed in the following table.
All parameters can be modified to target different designs. New HDL codes will be generated based on the updated parameters.
Table 1. Parameters for Variable Rate Decimation Filter Example
Parameter
Definition
ClockRate
The FPGA clock rate that should be the target fMAX
SampleRate
Input data sample rate
Period
The number of cycles available between unique input samples. Equals ClockRate/SampleRate and is a compile-time parameter
ChanCount
The number of input channels, and should not exceed Period
Rmax
The maximum decimation rate that the design supports
R
The current decimation rate, and should not exceed Rmax
L
The FIR kernel size, or the multiplier engine size. It represents the polyphase FIR filter length
vardownsampler.mdl – DSP Builder Advanced Blockset top-level test bench and design file for reconfigurable decimation filter
setup_vardownsampler.m – MATLAB script to configure initialization and parameters of vardownsampler.mdl
vardownsampler_bare.mdl – Design file based on vardownsampler.mdl. Some non-synthesizable test bench blocks are removed for register transfer level (RTL) generation
For more information on related features used in this design example in your project, go to:
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