Arria 10 Device Family - DE5a-Net FPGA Development Kit

From Terasic Inc.

Board Image

Block Diagram

Board Category: Production Ready Board, Development Kit

Components & Interface: Industry Standard: Ethernet, PCIE Edge, RS232

End Market: Broadcast, Computer & Storage, Industrial, Medical, Military, Test & Measurement, Wireline

Technology: ASIC Prototyping, DSP, Embedded Design, General Purpose, Interface Protocols

Arria Series: Intel® Arria® 10: Intel® Arria® 10 GX

Board Feature: General User IO: LED, Push Button


The Terasic DE5a-Net Arria® 10 GX FPGA Development Kit provides the ideal hardware solution for designs that demand high capacity and bandwidth memory interfacing, ultra-low latency communication, and power efficiency. With a full-height, 3/4-length form-factor package, the DE5a-Net is designed for the most demanding high-end applications, empowered with the top-of-the-line Intel® Arria 10 GX, delivering the best system-level integration and flexibility in the industry. The Arria 10 GX FPGA features integrated transceivers that transfer at a maximum of 12.5 Gbps, allowing the DE5a-Net to be fully compliant with version 3.0 of the PCI Express standard, as well as allowing an ultra low-latency, straight connections to four external 40G QSFP+ modules. Not relying on an external PHY will accelerate mainstream development of network applications enabling customers to deploy designs for a broad range of high-speed connectivity applications. For designs that demand high capacity and high speed for memory and storage, the DE5a-Net delivers with two independent banks of DDR3 SO-DIMM RAM, four independent banks of QDRII+ SRAM, high-speed parallel flash memory. The feature-set of the DE5a-Net fully supports all high-intensity applications such as low-latency trading, cloud computing, high-performance computing, data acquisition, network processing, and signal processing.

Order Information

Ordering Code
P0474$5520Buy Now

Development Kit Hardware Contents

  • On-Board USB Blaster II or JTAG header for FPGA programming
  • Four QSFP+ connectors; One RS422 expansion header
  • Two Independent DDR3 SODIMM Socket, Up to 8GB 800 MHz or 4GB 1066 MHz for each socket
  • Four Independent 550MHz QDRII+ SRAM, 18-bits data bus and 72Mbit for each
  • PCI Express (PCIe) x8 edge connector (includes Windows PCIe drivers)

Development Kit Software Contents

  • DE5a-Net System Builder
  • BSP(Board Support Package) for Intel® FPGA SDK OpenCL
  • Schematic and Mechanical Drawing
  • Memory & PCIe Reference Design
  • Flash and Oscillator Programming

Support Document

File Name
doc-us-dsnbk-42-1804382103-de5a-net-user-manual.pdfDE5a-Net User Manual1.0

Board Quality Metrics

Latest version of Quartus supported 15.1
Required Collateral Available
User Guide Y
Board Schematics Y
Reliability / Quality Assurance

Defects per Million Opportunities (DPMO)

Parts per Million (PPM)
Board Policy
Return Material Authorization (RMA) Policy If you want to make a return, please write an email to us within 7 days after you?ve received the product. The product must be unopened. (If the package is damaged upon receipt, please take photos and inform us immediately.) For more details, please visit:
RoHS Compliant Y
CE Compliant N. N/A
Conflict Mineral Policy Compliant
Test Plan Summary

Reference Designs from System CD for customers to access all the peripherals on board.

Additional Compliance
ISO 9000 & 9001

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.