Serial FPDP (sFPDP)
Block Diagram

Overview
sFPDP IP Core is based on ANSI/VITA 17.1-2015 Standards. This IP core provides a relatively simple protocol using maximum available data throughput with a minimum protocol for point-to-point data links. sFPDP links support a wide range of physical interfaces upto 10 gigabits per second multimode fiber.
Features
- Compliant with ANSI/VITA 17.1-2015 Serial FPDP standard
- Supported link speeds : - upto 10 Gbaud
- Data Frames supported: Unframed Data, Single Frame Data, Fixed Size Repeating Frame Data & Dynamic Size Repeating Frame Data
- Host-Bus interface : Parallel FPDP
- Receive FIFO watermark for STOP/GO signal generation
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2011 |
Latest version of Quartus supported | 18.0 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Parameterization GUI allowing end user to configure IP | Y |
IP core is enabled for OpenCore Plus Support | Y |
Source language | Verilog |
Testbench language | Verilog |
Software drivers provided | N |
Driver OS support | LINUX |
Implementation | |
User Interface | Avalon-MM |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | ModelSim DE 10.2 |
Hardware validated | Y. Altera Board Name Stratix IV GX |
Industry standard compliance testing performed | N |
If No, is it planned? | Y |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
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