Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
MAX Series: Intel® MAX® 10, MAX® V
Stratix Series: Stratix® IV, Stratix® V
iW-SDXC Host controller is compatible with the SD Physical Layer specification V3.0. The core supports 32 bit AHB LITE Host interface working at SOC interface frequency. The Host interface is compatible with the standard register set for the host controller as per SD host controller specification Version 3.0.
Compliant with SD specification version 3.0 & Supports 32 bit AHB LITE synchronous Host interface working at SOC interface frequency.
1-bit/4-bit modes of SD/SDIO supported. & One data Transmit FIFO with 32-bit write width and 256 depths.
SDR50 – SDR up to 100MHz 1.8V signaling & DDR50 – DDR up to 50MHz 1.8V signaling
One data Receive FIFO with 32-bit read width and 256 depths. & SDIO Interrupts, Suspend/Resume Operation and SDIO Read Wait Operation are supported.
Command buffers to store command index and argument. & Timeout monitoring for response and data operation.
Device Utilization and Performance
Intel® Cyclone® IV E
Logic Element combinational - 3570
Logic Element Registers - 1301
Embedded Multipliers 9 bit Elements -4
1. To give the latest SD specification version support SD 3.0
2. To enable memory storage (SDXC memory card) and input/ output (SDIO card) features in the product
3. Controller supports standard register set for the host controller
4. Core offers UHS-I mode of operation
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
ModelSim DE 10.2
Y. Altera Board Name Any Altera Development kit
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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