PCI-to-ISA Bridge
Block Diagram
Overview
The PCI-to-ISA bridge functions as a PCI target on the PCI bus. PCI transactions addressed to this target are forwarded to the ISA bus. If it is a read transfer, the core waits for all read data from the ISA slave and returns the data to the PCI bus. If it is a write transfer, the core posts the write data to its internal write buffer, terminates the PCI bus, and then writes the data to the ISA slave. With a typical PCI bus running at 33 MHz, this core operates the ISA bus at one-fourth the frequency of the PCI bus. The ISA bus operates at 8.33 MHz. The PCI-to-ISA bridge core supports 8-bit and 16-bit ISA bus devices, while the PCI bus is 32-bits wide. The core is capable of taking one PCI transfer and converting it into four or two transfers on the ISA bus. This megafunction sizes vary with features and customization. Eureka Technology can customize designs according to specific user requirements.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2000 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog; VHDL |
| Testbench language | Verilog; VHDL |
| Software drivers provided | N |
| Driver OS support | All PCI compatible |
| Implementation | |
| User Interface | AXI; Avalon-MM; Other: Generic/Wishbone/PLB |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Verilog/VHDL |
| Hardware validated | N. Altera Board Name NULL |
| Industry standard compliance testing performed | Y |
| If yes, which test(s)? | PCI Compliance |
| If yes, on which Altera device(s)? | Flex10K |
| If Yes, date performed | 01/01/1997 |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | Y |
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