lpm_ram_dp Intel® FPGA IP

Parameterized dual-port RAM Intel® FPGA IP. This Intel® FPGA IP is provided only for backward compatibility; instead, Intel recommends using the altsyncram Intel® FPGA IP. The lpm_ram_dp function uses DFFE primitives or latch arrays in MAX3000 and MAX7000 devices or if the USE_EAB parameter is set to "OFF". If you need extra features, you can use the altdpram Intel® FPGA IP. Intel strongly recommends using synchronous rather than asynchronous RAM functions.

  • The Quartus® Prime Compiler automatically implements this function in logic cells in MAX3000 and MAX7000 devices.
  • You can use the Assignment Editor to add, change, or delete assignments and assignment values for Intel® FPGA IP.
Note: More information is available on the lpm_ram_dp Intel® FPGA IP on the Altera website.