Input Ports

wren

Yes

Write enable input.

data[]

Yes

Data input to the memory.

Input port LPM_WIDTH wide.

wraddress[]

Yes

Write address input to the memory.

Input port LPM_WIDTHAD wide.

wrclock

No

Positive-edge-triggered clock for write operation.

If the wrclock port is used, it acts as the clock for write operation and functions as the clock signal to any registers present on the wraddress, wren, and data[] ports. For a single-clock synchronous design, you can tie rdclock and wrclock together.

wrclken

No

Clock enable for wrclock.

Used by all registers clocked by wrclock. For single-clock synchronous design, you can tie rdclock and wrclock together.

rden

No

Read enable input. Disables reading when low (0). The default is 1.

rdaddress[]

Yes

Read address input to the memory.

Input port LPM_WIDTHAD wide.

rdclock

No

Positive-edge-triggered clock for read operation.

Used for registered read ports, such as q, rdaddress, and rden. If the rdclock port is used, it acts as the clock for read operation and functions as the clock signal to any registers present on the rdaddress, rden, and q[] ports.

rdclken

No

Clock enable for rdclock.

Used by all registers clocked by rdclock. For single-clock synchronous design, you can tie rdclock and wrclock together.