altdqs Intel® FPGA IP

Parameterized bidirectional data strobe Intel® FPGA IP. The altdqs Intel® FPGA IP generates a group of DQS pins used to strobe read/write data in external DDR/FCRAM memory interfaces. The group of DQS pins use a common DLL to phase shift the read strobe. The altdqs Intel® FPGA IP implements one DLL and a number of user-specified DQS pins on one side of the device. The maximum number of DQS supported by a DLL depends on the device. The altdqs Intel® FPGA IP is available for Cyclone® IV devices.

Intel recommends instantiating this function with the IP Catalog.

  • For this Intel® FPGA IP, the IP Catalog generates output files with multiple entities or modules. The top-level entity or module is located at the bottom of the file.
  • To interface with the p and n-pins, you can instantiate your altdqs Intel® FPGA IP then instantiate an I/O buffer Intel® FPGA IP.
  • When you create your Intel® FPGA IP, you can use the IP Catalog togenerate a netlist for third-party synthesis tools.
Note: More information is available on the altdqs Intel® FPGA IP on the Altera website.