Input Ports

dqs_areset

No

Asynchronous set or reset signal for the DQS output and output enable registers.

dqs_datain_h[]

Yes

Data input port for the DQS output register which outputs on the rising edge of the outclk port.

Input port [NUMBER_OF_DQS-1..0] wide.

dqs_datain_l[]

Yes

Data input port for the DQS output register which outputs on the falling edge of the outclk port.

Input port [NUMBER_OF_DQS-1..0] wide.

dqs_sreset

No

Synchronous set or reset signal for the DQS output and output enable registers.

inclk

Yes

The system reference clock port that drives the DLL.

oe

No

Output enable for the DQS output registers.

The oe port defaults to VCC when enabled.

outclk

Yes

Clock to the DQS output and output enable registers.

outclkena

No

Clock enable port for the DQS output and oe registers.

The oe port defaults to VCC when enabled.

dll_reset[]

No

Data input for the DLL delay setting reset.

Values are "TRUE" and "FALSE".