Signal Configuration Pane (View Menu) (Signal Tap Logic Analyzer)

Allows you to specify signal configuration options for the Signal Tap Logic Analyzer. You can specify the sample depth and width, trigger conditions, buffer acquisition mode, clocks, signal sources, and outputs.

Clock:

Allows you to specify which signal in the selected instance to use as the Signal Tap Logic Analyzer clock. Each instance can have its own independent clock.

Data:

• Sample depth— Allows you to select the sample buffer depth in the selected instance of the Signal Tap Logic Analyzer (that is, the number of samples stored for each input signal).
• RAM Type— Allows you to select the RAM type for the acquisition buffer for all device families with multiple memory types.
• Segmented— Allows you to specify a segmented buffer for data acquisition.
• Pipeline Factor— Allows you to specify the number of pipeline registers to boost the fMAX of the Signal Tap Logic Analyzer.

Storage qualifier:

• Type— Allows you to specify the data capture mode.
• Input port— Allows you to specify the input port from which you want to capture data. This option is available only when you select Input Port in the Type list.
• Recorded data discontinuities— Allows you to view the data discontinuities in the waveform view. One extra memory bit is used for each sample.
• Disable storage qualifier— Allows you to turn off the storage qualifier to capture all data during acquisition without recompiling your design.

Trigger:

• Trigger flow control— Allows you to specify sequential or state-based flow control. The default setting is Sequential.
• Trigger position— Allows you to select a predefined trigger position. This option is configurable at runtime.
• Trigger conditions— Allows you to select the number of trigger conditions for all instances.