Trigger out

Allows you to enable the trigger output signal for the selected instance to synchronize external test equipment or another instance to an internal trigger event in the Signal Tap Logic Analyzer. You can trigger out to a device Pin, Node from the design, signal in a different Instance in the design, Hard Processor System (HPS) trigger in, or Hard Processor System (HPS) event. You must use an unused output pin to connect the external test equipment to the trigger output signal. You can generate hardware event entries in the HPS trace stream and assign event IDs with the Hard Processor System (HPS) eventtrigger. You can select more than one trigger out target.

You can specify the trigger output pin name in the Target list. The default trigger output pin, which you can rename, is auto_stp_trigger_out_n, where n represents the instance number.

This option is runtime configurable.

You can set the trigger output to generate a positive or negative signal in the Level list. The signal remains at the level you specify until the end of acquisition. The trigger output signal level changes a specific number of clock cycles after the trigger event occurs, based on the trigger output pin latency displayed in the Latency Delay box. The following table lists the options available in the Level list:


Trigger Output Signal Description

Active- High

Changes from low to high a specific number of clock cycles after the trigger event occurs.

Active- Low

Changes from high to low a specified number of clock cycles after the trigger event occurs.

The Latency Delay box displays the latency for the trigger output pin. This value can change depending on the Pipeline and Data delay settings on objects in the Advanced Trigger Condition Editor pane in the AdvancedTrigger tab.