Fitter I/O Reports

Reports all the pins and their I/O standards Definition for the target device family.

The pin name and the symbol in the pin name represent the type of pin and its function as follows:

• N.C. (No Connect) shows a pin that has no internal connection to the device.
• VCCINT shows a dedicated power pin, which must be connected to VCC internal signal.
• VCCIO shows a dedicated power pin, which must be connected to VCC I/O bank.
• GND shows a dedicated ground pin or unused dedicated input, which must be connected to GND.
• GNDINT shows a dedicated ground pin or unused dedicated input, which must be connected to GND internal signal.
• GNDIO shows a dedicated ground pin which must be connected to GND.
• RESERVED shows an unused I/O pin, which must be left unconnected.
• ^ character in name shows a dedicated configuration pin.
• + character in name shows a reserved configuration pin that is tri-stated in user mode.
• * character in name shows a reserved configuration pin that drives out in user mode.
• # character in name shows a JTAG BST/in-system programming or configuration pin. The JTAG inputs TMS and TDI should be tied to VCC, and TCK should be tied to GND when not in use.
• & character in name shows a JTAG pin used as an I/O pin. When used as I/O pins, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
• GND+ shows an unused input. This pin should be connected to GND. It may also be connected to a legal signal on the board if that signal is required for a different revision of the design.
• GND* shows an unused I/O pin that drives out.

Reports the following information about all bidirectional pins used in the device:

• Name shows the name of the pin.
• Pin # shows the pin number.
• I/O Bank shows the number of the I/O bank in which the pin is located.
• Migration Pin # shows the pin number of the largest compatible migration device. This column appears only if turn on Base the Pin-Out File (.pin) and floorplan package views on the largest selected SameFrame device in the Migration Devices dialog box, which is available from the Device dialog box of the Settings dialog box.
• X coordinate shows the X coordinate location of the input pin.
• Y coordinate shows the Y coordinate location of the input pin.
• Cell number shows the cell number that corresponds to the input pin.
• Combinational Fan-Out shows the number of fan-outs to combinational logic for the input pin.
• Registered Fan-Out shows the number of fan-outs to registered logic for the input pin.
• Col. shows the column number to which the pin is assigned.
• Fan-Out shows the fan-out for the pin.
• Global shows whether the pin is a global source.
• I/O Register shows whether the pin uses an I/O register to register either an input or output signal.
• Input Register shows whether the pin uses an input register to register an input signal.
• Output Register shows whether the pin uses an output register to register an output signal.
• Output Enable Register shows whether the pin uses an output enable register.
• Use Local Routing Input shows whether the pin uses a local routing resource to route to the adjacent LAB.
• Power Up High shows, if a peripheral register exists, whether the pin powers up high because the Power-Up Level logic option is applied to the pin.
• Slow Slew Rate shows whether the Slow Slew Rate logic option is applied to the pin.
• Delay Chain shows whether the Auto Delay Chains logic option is applied to the pin.
• PCI I/O Enabled shows whether the PCI I/O logic option is applied to the pin.
• Single-Pin CE shows whether the clock enable signal is driven from the local interconnect.
• Open Drain shows whether the Auto Open-Drain Pins option is applied to the pin.
• Bus Hold shows whether the Enable Bus-Hold Circuitry logic option is applied to the pin.
• Weak Pull Up shows whether the Weak Pull-Up Resistor logic option is applied to the pin.
• I/O Standard shows the I/O standards Definition is applied to the pin.
• Current Strength shows the strength of the current, in mA, on the pin if the Current Strength logic option is applied to the pin.
• Termination shows whether the Termination logic option is applied to the output pin.
• Output Buffer Delay shows the delay in ps.
• Output Buffer Control shows the setting for the programmable output buffer delay and which edge is controlled (Off | Rising | Falling | Both), on a single-ended output buffer.
• Location Assigned By shows whether the pin location was assigned by the Fitter or the user.
• Load shows the user-specified capacitance, in pF, on the pin.
• Output Enable Source lists the output enable source pin.
• Output Enable Group lists the output enable group.

Reports the following information about dual purpose pins, dedicated pins, and JTAG pins:

• Location shows the location name of the specified pin.
• Pin Name shows the auxiliary function name of the pin.
• Reserved As shows the use for which the pin has been reserved.
• User Signal Name shows the name of the signal for which the pin is the source.
• Pin Type lists the type of pin.

Reports the following information about the input pins for the device:

• Name shows the name of the pin.
• Pin # shows the pin number.
• I/O Bank shows the number of the I/O bank containing the pin.
• X coordinate, Y coordinate shows the X coordinate location of the input pin.
• Cell number shows the cell number that corresponds to the input pin.
• Combinational Fan-Out shows the number of fan-outs to combinational logic for the input pin.
• Registered Fan-Out shows the number of fan-outs to registered logic for the input pin.
• Row shows the row to which the pin is assigned.
• Fan-Out shows the fan-out for the pin.
• Global shows whether the pin is a global source.
• Input Register shows whether the pin uses an input register to register an input signal.
• Use Local Routing Input shows whether the pin uses a local routing resource to route into the adjacent LAB.
• Power Up High shows, if a peripheral register exists, whether the pin powers up high because thePower-Up Levellogic option is applied to the pin.
• Delay Chain shows whether the Auto Delay Chains logic option is applied to the pin.
• PCI I/O Enabled shows whether the PCI I/O logic option is applied to the pin.
• Single-Pin CE shows whether the clock enable signal is driven from the local interconnect.
• Open Drain shows whether the Auto Open-Drain Pins option is applied to the pin.
• Bus Hold shows whether the Enable Bus-Hold Circuitry logic option is applied to the pin.
• Weak Pull Up shows whether the Weak Pull-Up Resistor logic option is applied to the pin.
• I/O Standard shows the I/O standards Definition is applied to the pin.
• Termination shows whether the Termination logic option is applied to the input pin.
• Location Assigned By shows whether the pin location was assigned by the Fitter or the user.

Reports information about the I/O bank Definition usage for the device including the I/O Bank number, Usage (<number> / <total available> (<percent used> %)), VCCIO Voltage, and VREF Voltage.

Reports the following information about the I/O standards Definition, load, and termination resistance, measured on the reported tco (clock to output delay) Definition for the output pins in the device.

• I/O Standard shows the I/O standard for which the tCO was measured.
• Load shows the load, in pF, measured on the tCO.
• Termination Resistance shows the termination resistance, in Ω, measured on the tCO, and the amount of resistance that is parallel and serial, if applicable. Resistance is parallel unless otherwise specified.

Reports the following information about the output pins in the device:

• Name shows the name of the pin.
• Pin # shows the pin number.
• I/O Bank shows the number of the I/O bank containing the pin.
• X coordinate, Y coordinate shows the X and Y coordinates of the output pin.
• Cell number shows the cell number that corresponds to the output pin.
• Row shows the row number to which the pin is assigned.
• Output Register shows whether the pin uses an output register to register an output signal.
• Output Enable Register shows whether the pin uses an output enable register.
• Use Local Routing Output shows whether the pin uses a local routing resource to route into the adjacent LAB.
• Power Up High shows, if a peripheral register exists, whether the pin powers up high because the Power-Up Level logic option is applied to the pin.
• Slow Slew Rate shows whether the Slow Slew Rate logic option is applied to the pin.
• Delay Chain shows whether the Auto Delay Chains logic option is applied to the pin.
• PCI I/O Enabled shows whether the PCI I/O logic option is applied to the pin.
• Single-Pin OE shows whether the output enable signal is driven from the local interconnect.
• Single-Pin CE shows whether the clock enable signal is driven from the local interconnect.
• Open Drain shows whether the Auto Open-Drain Pins option is applied to the pin.
• TRI Primitive shows whether the TRI primitive tri-state buffer is applied to the pin.
• Bus Hold shows whether the Enable Bus-Hold Circuitry logic option is applied to the pin.
• Weak Pull Up shows whether the Weak Pull-Up Resistor logic option is applied to the pin.
• I/O Standard shows the I/O standards Definition assigned to the pin.
• Current Strength shows the strength of the current, in mA, on the pin if the Current Strength logic option is applied to the pin.
• Termination shows whether the Termination logic option is applied to the bidirectional pin.
• Output Buffer Pre-emphasis shows whether control of programmable pre-emphasis is applied to differential output pins, which helps compensate for high frequency losses. This option is ignored if it is applied to anything other than an output or bidirectional pin, or a top-level design entity containing output or bidirectional pins.
• Voltage Output Differential (VOD) shows whether control of programmable VOD is applied to differential output pins. This option is ignored if it is applied to anything other than an output or bidirectional pin, or a top-level design entity containing output or bidirectional pins.
• Output Buffer Delay shows the delay in ps.
• Output Buffer Control shows the setting for the programmable output buffer delay and which edge is controlled (Off | Rising | Falling | Both), on a single-ended output buffer.
• Location Assigned By shows whether the pin location was assigned by the Fitter or the user.
• Load shows the user-specified capacitance, in pF, on the pin.
• Output Enable Source lists the output enable source pin.
• Output Enable Group lists the output enable group.

Lists the SignalProbe target, source node name, location, number of pipeline registers, clock name and I/O standard.

You can right-click a SignalProbe path in the SignalProbe Fitting Results report and click Locate to view a list of options available for the selected path.

Reports summary information for the altmemphy megafunction including Name, Type, Direction, Pin Location, X Location, Y Location, Z Location, DQS Bus Width, I/O Edge, I/O Bank, Input DQS Frequency, Max DQS Frequency, I/O Standard, Current Strength, Output Termination, DQS Delay, and Delay Chain Setting.