Power-Up Level logic option

A logic option that causes a register to power up with the specified logic level, either High (1) or Low (0). If this option is specified for an input pin, it is automatically transferred to the register that is driven by the pin if the following conditions are present:

• There is no intervening logic, other than inversion, between the pin and the register.
• The input pin drives the data input of the register.
• The input pin does not fan-out to any other logic.

If this option is specified for an output or bidirectional pin, it is automatically transferred to the register that feeds the pin if:

• There is no intervening logic, other than inversion, between the register and the pin.
• The register does not fan-out to any other logic.

You can assign this option to any register, registered logic cell WYSIWYG primitive, or to a pin with any logic configuration other than those described above. If this option is assigned to a registered logic cell WYSIWYG primitive, you must turn on the Perform WYSIWYG Primitive Resynthesis logic option for it to take effect. You can also assign this option to a design entity containing registers if you want to set the power level for all registers in the design entity. In order for the register to power up with the specified logic level, the Compiler may perform NOT Gate Push-Back on the register. This option is available for all Altera devices supported by the Quartus^® Prime Standard Edition software.