Auto Delay Chains logic option

A logic option that allows the Fitter to choose the optimal delay chain setting from the Decrease Input Delay to Input Register, Decrease Input Delay to Internal Cells, Decrease Input Delay to Output Register, Increase Delay to Output Enable Pin, Increase Delay to Output Pin, Increase Input Clock Enable Delay, Increase Output Clock Enable Delay, Increase Output Enable Clock Enable Delay, or Increase tzx Delay to Output Pin logic options to meet tSU and tCO timing requirements for all I/O elements. Turning on this option may reduce the number of tSU violations while introducing a minimal number of tH violations. Turning on this option does not override delay chain settings on individual nodes.

This option is useful for automatically meeting tSU timing requirements by adjusting the delay chain setting, rather than by adjusting the timing requirements on individual pins and performing multiple compilations to get the optimal delay for the design.

This option is a project-wide option. This option is available for all Altera devices supported by the Quartus^® Prime Standard Edition software except MAXII, MAX3000, and MAX7000 devices.