A logic option that directs the Quartus® Prime Standard Edition software to perform automatic insertion of pipeline stages for asynchronous clear and asynchronous load signals during fitting to increase circuit performance. This option is useful for asynchronous signals that are failing recovery and removal timing because they feed registers using a high-speed clock.
The following examples illustrate typical situations where automatic asynchronous signal pipelining is used.
To run the automatic asynchronous signal pipelining algorithm, the signal must meet the following requirements:
This option is available for supported device(Arria series, Cycloneseries, MAXII, MAXV, and Stratixseries) families.
Scripting Information |
Keyword: physical_synthesis_asynchronous_signal_pipelining Settings:on | off *default |