Netlist Optimizations logic option

A logic option that specifies whether the Compiler should perform advanced netlist optimizations, such as gate-level retiming or physical synthesis, on the specified node or entity.

This option is useful for preserving I/O timing on specific pins and registers in a design where you want to perform netlist optimization. This option is also useful for preserving the synthesis of a specific node or entity, for example, preserving the name of a register.

This option is ignored for gate-level retiming if it is applied to anything other than a register or a design entity containing registers. For synthesis and fitting, this option is ignored if it is applied to anything other than a logic cell or design entity. This option is available for all Altera devices supported by the Quartus^® Prime Standard Edition software except MAX3000 and MAX7000 devices.