Setting Options for EDA Tools

In the EDA Tool Settings pages of the Settings dialog box, you can specify options for the EDA tools you want to use. You can direct the Quartus^® Prime Standard Edition software to run a synthesis tool to synthesize the design as part of a normal compilation. You can also direct the Quartus^® Prime Standard Edition software to run a simulation or timing analysis tool automatically after compilation. You can specify additional options for input and output files in the following pages that are under the EDA Tool Settings page:

• In the More EDA Netlist Writer Settings dialog box you can specify settings for generating functional simulation netlist files.
• In the Design Entry and Synthesis page, you can specify an EDA design entry or synthesis tool and specify EDA tool input settings, including specifying a Library Mapping File (.lmf) Definition for processing EDIF Input Files, VHDL Design Files, Verilog Design Files, Verilog Quartus Mapping Files, and AHDL Text Design Files that were generated by other design entry or synthesis tools.
• In the Simulation page, you can specify EDA tools for simulation and specify HDL output settings for generating Verilog, SystemVerilog, and VHDL Output Files and SDF Output Files for use with other simulation or timing analysis tools. You can also specify settings for running the Mentor Graphics ModelSim, ModelSim-Altera, Cadence Incisive Enterprise Simulator, VCS, or VCS MX simulation software with a test bench.
• In the Board-Level page, you can specify various board-level tools. You can generate files for use in several different kinds of board-level verification processes, including Stamp model files Definition for timing verification with the Mentor Graphics TAU software, FPGA Xchange-Format File (.fx) Definition for use with Mentor Graphics I/O Designer software, PartMiner edaXML-Format File (.xml) Definition for symbol generation in the Mentor Graphics DxParts software, and IBIS Output File (.ibs) Definition and HSPICE Simulation Deck File (.sp) Definition for signal integrity analysis.
• In the Formal Verification page, you can specify an EDA formal verification tool. You can generate files for use in formal verification of a design with the Cadence Encounter Conformal software.