About the Netlist Viewers

The RTL Viewer, State Machine Viewer, and Technology Map Viewer allow you to view schematic representations of the internal structure of your designs. Each viewer displays a unique view of the netlist, and allows you to view different internal structures.

The RTL Viewer allows you to view a schematic of the design netlist after Analysis & Elaboration and netlist extraction, but before Quartus II synthesis and fitting optimizations. This view is not the final structure of the design, because not all optimizations are included; instead it is the closest possible view to the original design. If the design uses integrated synthesis, this view shows how the Quartus II software interprets the design files; if you are using a third-party EDA synthesis tool, this view shows the netlist as written by the EDA synthesis tool. When processing the netlist, the RTL Viewer automatically performs the following optimizations:

Removes internally used tri-state buses.
Connects bidirectional pins directly to their sources.
Removes single input nodes.
Converts NOT gates to bubble inversions.
Removes registers without fan-in or fan-out.
Merges chains of equivalent combinational gates into a single gate.

The Technology Map Viewer allows you to view a low-level, technology-specific schematic of the design netlist after fitting or after Analysis & Synthesis. You can access the post-fitting view of the schematic with the command; or you can access the post-mapping view of the schematic, regardless of the synthesis tool you use, with the command. When opened from a timing path in the Timing Analyzer report, the Technology Map Viewer also displays detailed timing delay information for the timing path.

In the RTL Viewer and Technology Map Viewer, you can search the design netlist in the Find pane. You can view the properties of a selected entity in the Properties pane.

The State Machine Viewer provides a high-level view of finite state machines in the design and displays the internal structure of state machines in the design, including a more detailed view of the fan-in and fan-out of individual state nodes. The State Machine Viewer also displays the node transitions in table format.

The RTL Viewer and Technology Map Viewer provides a hierarchy list that displays a representation of the project hierarchy and links to a schematic view that displays the components of the design element you want to examine. The hierarchy list expands as you navigate through the schematic view. You can use the Back and Forward commands to display the previously viewed design views. Up to ten views are cached. You can also open the implementation of a design instance by double-clicking an instance in the hierarchy list.

In the schematic view, different default colors are used to discern different design elements.

You can change the color assigned to each design element in the schematic view by clicking Color Settings and changing the color scheme in the Colors pane.

You can traverse the design hierarchy for all non-encrypted design instances. Encrypted design instances may include intellectual property (IP) cores, MegaCore functions, or other logic purchased from third-party EDA vendors for which you do not have a license to view the internal logic. If you select a design element in the schematic view, it is highlighted in red; if you select a signal path, the entire path is highlighted in red.

If the schematic is large, the schematic is divided into multiple pages. When the schematic is divided into multiple pages, use the Page <n> of <n> control to display the previous and next sequential pages for the current design view. If the schematic is divided into multiple pages and you want to display the source page of the selected connector pin, or the pages it connects to, right-click the connector pin and then click the appropriate Filter command.

The RTL Viewer and Technology Map Viewer allow you to isolate selected design elements and analyze portions of the design by filtering unrelated nodes from the schematic view. If you want to view all of the lower level nodes and connections below the currently displayed hierarchy level, right-click anywhere in the schematic view and then click Expand to Upper Hierarchy. The nodes in the RTL Viewer and Technology Map Viewer use the same symbols used in the Block Editor, as well as non-standard symbols.

The State Machine Viewer provides a graphical representation of the states and their related transitions, as well as a state transition table that displays the condition equation for each of the state transitions. After running Analysis & Synthesis, you can also view encoding information for the state transitions in the State Machine Viewer. The state nodes are arranged horizontally in the state diagram view with the initial state— that is, the state node that receives the reset signal— in the leftmost position. Nodes that connect to logic outside the state machine instance are represented by a double circle. The state transition is represented by a transition arc with an arrow pointing in the direction of the transition; further, transitions that traverse from left to right in the state machine view appear above the state nodes, while transitions that traverse from right to left state appear below the state nodes. If the state node transition traverses to itself, the transition arc appears on the right side of the node. The length of the transition arc between one state and another is relative to the actual distance between the source and destination state nodes.

If you select a state node in the state diagram view and you turn on the Highlight Fan-In or Highlight Fan-Out command, the respective fan-in or fan-out from the node is highlighted in red. Also, when you select a node or transition arc in the state diagram view, the matching state node or equation conditions in the state transition table are highlighted; conversely, when you select a state node or equation condition in the state transition table, the corresponding state node or transition arc is highlighted in the state diagram view.

The RTL Viewer and Technology Map Viewer are useful for finding errors instantiated in Verilog HDL or VHDL source code after the code is compiled. For example, the Verilog HDL or VHDL source code may contain a typographical error, such as:out1 <= a & b; out2 <= outt1 & c;

It may be difficult for you to find the error in the source code, but the error is easier to see when the RTL Viewer or Technology Map Viewer displays an unconnected pin.

You can use the RTL Viewer and Technology Map Viewer to confirm that all design components are generated properly and that all of the connections are correct. For example, if you wrote Verilog HDL or VHDL source code containing a FOR loop that instantiates an array of adders, the RTL Viewer or Technology Map Viewer displays all of the design components and connections, so you can confirm that the FOR loop functions properly.

You can use the Technology Map Viewer to confirm that the Verilog HDL or VHDL source code is written correctly and functions as intended. For example, if you wrote Verilog HDL or VHDL source code to implement inferred RAM, you can use the Technology Map Viewer to make sure that the RAM is inferred, that the correct type of RAM is inferred, and that no extra registers are added before the RAM.

The State Machine Viewer allows you to verify the states in the design, the transitions between them, and the encoding of the state machines in an easy-to-read format. Much like the corresponding RTL Viewer and Technology Map Viewer, the State Machine Viewer is useful for finding errors instantiated in Verilog HDL or VHDL source code. You can easily see any diversion from the design intended in the source code in the graphical representation of the state machines and their transitions.