The State Machine Editor allows you to create graphic representations of state machines for use in your design. Creating state machines using the State Machine Editor allows you to describe complex control logic and state machines used, for example, in DSP processors, without the need for writing lengthy and complex Verilog HDL or VHDL source code. You can, however, generate a Verilog Design File (.v) or VHDL Design File (.vhd) directly from the State Machine Editor with the Generate HDL File command.

User Interface and Functionality

The State Machine Editor provides a state machine diagram view where you can view the state diagram you created with the State Machine wizard or the drawing tools provided. The Input Table window and Output Table window display the input and output ports in the state machine; you open these windows with the Input Ports List and Output Ports List commands.

The drawing tools provided with the State Machine Editor, available on the toolbar, comprise a State Tool used to create new states, a Transition Tool for drawing transitions between states, Input Port Tool and Output Port Tool used to create new ports, and a Rubberbanding Tool for automatic transition routing.

You cannot drag and drop the ports into the state machine diagram view.

You can view the properties of the individual states and transitions in their corresponding Properties dialog box. You can view the properties of the entire state machine in the State Table.

The State Machine Editor performs preliminary design language syntax verification in real-time.