The SignalProbe feature allows you to route user-specified signals to output pins without affecting the existing fitting in a design. Using the SignalProbe feature allows you to investigate internal device signals without performing a full compilation.

For supported device(Arria V, Cyclone III, Cyclone IV, Cyclone V, MAX II, Stratix III, Stratix IV, and Stratix V) families SignalProbe pins are added to the post-compilation netlist and implemented as engineering change orders (ECOs) and can be viewed in the Change Manager. Any pin assignments, such as I/O standard and pin reservation information, are written to the Quartus II Settings File (.qsf), but any SignalProbe creation and connection information can be viewed only in the Change Manager or SignalProbe Pins dialog box, not as an assignment in the Quartus II Settings File.

When you select pins to be used as SignalProbe pins, you can use I/O pins reserved as SignalProbe outputs prior to a compilation, or you can use unused I/O pins as SignalProbe outputs in a post-compilation design . After you assign an I/O pin as a SignalProbe output pin, you can assign a SignalProbe source to the output pin. You must assign a SignalProbe source from a post-compilation design, but the source cannot be a dedicated clock, a DDIO output pin, or a group or bus, and cannot have a carry or cascade chain fan-out. You can use the SignalProbe filter in the Node Finder to find a list of available SignalProbe sources. You can assign only one SignalProbe source to a SignalProbe output pin, but you can have multiple SignalProbe sources and SignalProbe output pins.

After you assign sources to SignalProbe output pins, you can route the sources to the pins by performing a SignalProbe compilation. A SignalProbe compilation compiles a design without affecting the fit in the design unless absolutely necessary, and routes the SignalProbe signals faster than a normal compilation. Once you complete your investigation of signals, you can remove all or some of the SignalProbe pins.

You can use register pipelining to register one or more SignalProbe signals with a user-specified clock and a user-specified number of registers, allowing you greater control over the SignalProbe output signals, for example, to synchronize multiple SignalProbe signals.

You can also use the SignalProbe feature with Tcl. With Tcl commands, you can add and remove SignalProbe connections and sources, perform a SignalProbe compilation on a design.