About Optimizing the Design

Design optimization for achieving the highest quality of results—including reduced resource usage, improved timing performance, reduced compilation times, and optimized power consumption—is an essential part of circuit design. The Quartus II software provides many techniques for design optimization. A particular set of optimization techniques may not always improve design results; the set of optimization techniques that achieve the highest quality of results is unique to each design. You should compile the design without any design optimization to obtain a baseline from which you can improve the quality of results. Any design optimization may result in a trade off between speed, area, and power consumption.

If the design does not fit into the target device, you can try to optimize resource utilization using various options and settings in the Quartus II software. You can reduce the number of logic cells in the design by using register packing to combine the function of logic cells with the Auto Packed Registers logic option. Reducing the number of logic cells can have a negative effect on the speed of the design.

If you use strict LogicLock region or location assignments, the design may not fit into the target device. You can use the Chip Planner to view congested areas of the device and then remove the location and LogicLock assignments. You can reduce the number of logic cells used in the design with the Restructure Multiplexers logic option.

If the design does not fit because of a lack of memory resources, you may be able to use different types of memory blocks in the device to obtain a fit. You may also be able to adjust the DSP block use.

You can optimize the design for area rather than speed using the Optimization Technique logic option. If your design uses a netlist generated by an EDA tool, you can resynthesize some or all of the WYSIWYG primitives in the design for better area or performance with the Perform WYSIWYG Primitive Resynthesis logic option.

You can improve timing results by optimizing I/O timing; however, changes to I/O timing can affect fMAX results. You can use the various optimization settings on the Settings dialog box to meet timing requirements. You can implement registers in an I/O cells that have a fast, direct connection with I/O pins with the Fast Input Register, Fast Output Register, and Fast Output Enable Register logic options.

You can implement delay chains in the design to help meet timing requirements. The Auto Delay Chains logic option allows the Quartus II software to automatically implement delay chains, or you can choose from the other delay chain logic options. You can also use the Resource Property Editor or Chip Planner to view and change delay chain settings.

After optimizing the design for I/O timing, if the design does not achieve timing closure, you can further improve timing results by optimizing fMAX timing. You can optimize the design for speed rather than area using the Physical Synthesis Optimizations page of the Settings dialog box. You can also turn off the Restructure Multiplexers logic option to improve timing results.

To improve timing results due to the fan-out of registers, use the Maximum Fan-Out logic option to control the number of destinations for a node so that the fan-out count does not exceed a specified value. You can also duplicate registers with the Manual Logic Duplication logic option to redirect fan-out.

To improve routing delays and constrain logic to certain areas of the device you can make LogicLock assignments.

Using Settings dialog box to reduce fitting time, or you can use the Placement Effort Multiplier logic option to reduce the amount of time the Fitter spends in placement. Similarly, you can identify and reduce areas of routing congestion with the Chip Planner to reduce routing time, or you can use the Routing Effort Multiplier logic option to reduce the amount of time the Fitter spends in routing.