Back-Annotating Assignments for a Project

Back-annotation allows you to copy device and resource assignments made during compilation into the , thereby preserving the current fit for future compilations. The back-annotation process copies the project's routing assignments into a You can use the Back-Annotate Assignments dialog box (Default type) to preserve pin, cell, routing, or device assignments, or you can use the Back-Annotate Assignments dialog box (Advanced type) to preserve LogicLock regions and employ more advanced back-annotation options.

If you have not already done so, compile a design.
On the Assignments menu, click Back-Annotate Assignments.
In the Back annotation type list, select Default.
Under Assignments to back-annotate, turn on or off one or more categories of assignments for back annotation, and select any optional sub categories or filters.
If your compilation results include Netlist Optimizations logic options, specify a Verilog Quartus Mapping File (.vqm) under Save intermediate synthesis results to preserve netlist optimizations.
Click OK.

If you have not already done so, compile a design.
On the Assignments menu, click Back-Annotate Assignments.
Under Assignments to back-annotate, turn on or off one or more categories of assignments for back annotation, and select any optional sub categories or filters.
If you turned on LogicLock regions back-annotation and want to filter the LogicLock regions that are back-annotated, click Region Filter and select the regions you want to back-annotate.
If you turned on Nodes back-annotation and want to filter path-based and wildcard node assignments that are back-annotated, click Node Filter and specify the path or wildcard assignments.
If your compilation results include Netlist Optimizations logic options, specify a Verilog Quartus Mapping File (.vqm) under Save intermediate synthesis results to preserve netlist optimizations.
Click OK.