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Running a Timing Analysis (TimeQuest Timing Analyzer) |
You can use the TimeQuest Timing Analyzer to validate the timing performance of all logic in a design, and to guide logic placement by the Fitter. You can direct the Compiler to automatically use the TimeQuest analyzer during the compilation process, or you can run the TimeQuest analyzer separately. If you change any settings or source files that might affect fitting, you must regenerate and load the timing netlist to include those changes in a TimeQuest analysis.
You can specify SDC timing constraints and exceptions with the commands in the TimeQuest analyzer Constraints menu or by creating a Synopsys Design Constraints File (.sdc).
On the Tools menu, click TimeQuest
Timing Analyzer.
In the Tasks
pane, a checkmark appears next to Open
Project to signify that the Quartus
II Project File (.qpf) open in the Quartus II software is also
open in the TimeQuest analyzer.
To load the timing netlist in the TimeQuest analyzer, in the Tasks pane, double-click Create Timing Netlist.
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Note: If you want to specify custom timing netlist settings such as the netlist type or timing model, click Create Timing Netlist on the Netlist menu. |
To specify timing constraints or exceptions, perform one of the following:
Set timing constraints or exceptions with the commands in the Constraints menu.
Load an existing Synopsys Design Constraints File (.sdc) by clicking Read SDC File on the Tasks pane.
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Note: If you recompile the design, you must delete and then re-create the timing netlist before running the TimeQuest analyzer. |
In the Tasks pane, double-click Update Timing Netlist.
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Note: You can right-click any command in the Tasks pane and click Start Again to run that command again in the TimeQuest Timing Analyzer task flow. |
