Delivering low network latency is critical to success for Financial Service Industry applications. To achieve this goal, Algo-Logic Systems’ Ultra-Low-Latency (ULL) MAC was designed to minimize roundtrip latency.


The ULL MAC is compatible with the Intel FPGA PAC D5005 platform and supports SERDES rates of 10.3125 Gbps while bypassing all PCS and excessive buffering features.

 

Key Features

  • Ultra-low-latency round-trip (fiber-to-fiber or gate-to-gate) for 10 Gigabit Ethernet, first-bit to first-bit
  • Reconciliation sub-layer implementation compliant with IEEE802.3
  • Local fault and remote fault detection and handling
  • Frame Check Sequence (FCS) insertion and verification at line rate
  • Automatic transmit padding, jumbo frame support, transmit and receive statistics counters
  • Low gate count

 

Low-Latency Data Mover Framework from Algo-Logic with Intel® FPGA PAC D5005

 

If you would like to learn more and get access to this IP, please contact Algo-Logic at intelsupport@algo-logic.com with the following information:

  • Customer name
  • Customer email
  • Customer address

Algo-Logic Systems' TOE (TCP Offload Engine) provides a full, reliable streaming network stack for the Intel FPGA PAC D5005 running in Financial Services Industry applications. It allows customers to be directly connected to Internet Protocol (IP) interfaces by opening, maintaining, and closing TCP Connections via Ethernet to other hardware or software endpoints.


The TOE delivers high performance with the ultra-low latency required for demanding Financial Services applications. It runs at the full 10 Gigabit Ethernet line rate with a clock speed synchronous with a MAC and application processing logic.


Algo-Logic’s TOE has been deployed in customer applications including pre-trade risk-checks and complete tick-to-trade applications.



Key features and Use-Cases

  • Full TCP/IP stack in FPGA logic
    • Layer 1: IEEE802.3
    • Layer 2: IEEE802.3, ARP
    • Layer 3: IPv4 and ICMP
    • Layer 4: TCP
  • Ultra-low latency
    • Optional cut-through for receive (RX) and transmit (TX) data.
  • Parameters
    • Retransmission timeouts
    • Size of shared on-chip retransmission buffer
    • Option for fast retransmission
    • Limits on retransmissions
    • TX Rewind
  • High network bandwidth
    • Multiple instances allow for more than 200 Gbps to a single FPGA device
  • Control registers
    • Configurable over network or PCIe
  • TCP option support: MSS, window scaling, timestamps
  • Robust flow control and error control

 

 

Low-Latency Data Mover Framework from Algo-Logic with Intel® FPGA PAC D5005

 

If you would like to learn more or get access to the evaluation version of this IP, please contact Algo-Logic at intelsupport@algo-logic.com with the following information:

  • Customer name
  • Customer email
  • Customer address

+ Contact local Intel® sales or distributors for Algo-Logic TOE IP commercial license