Delivering low network latency is critical to success for Financial Service Industry applications. To achieve this goal, Algo-Logic Systems’ Ultra-Low-Latency (ULL) MAC was designed to minimize roundtrip latency.
The ULL MAC is compatible with the Intel FPGA PAC D5005 platform and supports SERDES rates of 10.3125 Gbps while bypassing all PCS and excessive buffering features.
- Ultra-low-latency round-trip (fiber-to-fiber or gate-to-gate) for 10 Gigabit Ethernet, first-bit to first-bit
- Reconciliation sub-layer implementation compliant with IEEE802.3
- Local fault and remote fault detection and handling
- Frame Check Sequence (FCS) insertion and verification at line rate
- Automatic transmit padding, jumbo frame support, transmit and receive statistics counters
- Low gate count
Low-Latency Data Mover Framework from Algo-Logic with Intel® FPGA PAC D5005
If you would like to learn more and get access to this IP, please contact Algo-Logic at firstname.lastname@example.org with the following information:
- Customer name
- Customer email
- Customer address