Clock Manager Module Summary

Registers in the Clock Manager module

Base Address: 0xFFD04000

Register Address Offset	Bit Fields
`ctrl` `0x0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`													`ensfmdwr` `RW 0x1`	`Reserved`	`safemode` `RW 0x1`
`bypass` `0x4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`perpllsrc` `RW 0x0`	`perpll` `RW 0x1`	`sdrpllsrc` `RW 0x0`	`sdrpll` `RW 0x1`	`mainpll` `RW 0x1`
`inter` `0x8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`sdrplllocked` `RO 0x0`	`perplllocked` `RO 0x0`	`mainplllocked` `RO 0x0`	`sdrplllost` `RW 0x0`	`perplllost` `RW 0x0`	`mainplllost` `RW 0x0`	`sdrpllachieved` `RW 0x0`	`perpllachieved` `RW 0x0`	`mainpllachieved` `RW 0x0`
`intren` `0xC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`										`sdrplllost` `RW 0x0`	`perplllost` `RW 0x0`	`mainplllost` `RW 0x0`	`sdrpllachieved` `RW 0x0`	`perpllachieved` `RW 0x0`	`mainpllachieved` `RW 0x0`
`dbctrl` `0x10`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`ensfmdwr` `RW 0x1`	`stayosc1` `RW 0x1`
`stat` `0x14`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`busy` `RO 0x0`
`Main PLL Group`
`vco` `0x40`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`regextsel` `RW 0x1`	`outreset` `RW 0x0`						`outresetall` `RW 0x0`	`Reserved`		`denom` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`numer` `RW 0x1`													`pwrdn` `RW 0x1`	`en` `RW 0x0`	`bgpwrdn` `RW 0x1`
`misc` `0x44`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`	`saten` `RW 0x1`	`fasten` `RW 0x0`	`bwadj` `RW 0x1`												`bwadjen` `RW 0x0`
`mpuclk` `0x48`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`cnt` `RW 0x0`
`mainclk` `0x4C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`cnt` `RW 0x0`
`dbgatclk` `0x50`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`cnt` `RW 0x0`
`mainqspiclk` `0x54`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`cnt` `RW 0x3`
`mainnandsdmmcclk` `0x58`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`cnt` `RW 0x3`
`cfgs2fuser0clk` `0x5C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`cnt` `RW 0xF`
`en` `0x60`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`						`s2fuser0clk` `RW 0x1`	`cfgclk` `RW 0x1`	`dbgtimerclk` `RW 0x1`	`dbgtraceclk` `RW 0x1`	`dbgclk` `RW 0x1`	`dbgatclk` `RW 0x1`	`l4spclk` `RW 0x1`	`l4mpclk` `RW 0x1`	`l3mpclk` `RW 0x1`	`l4mainclk` `RW 0x1`
`maindiv` `0x64`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`						`l4spclk` `RW 0x0`			`l4mpclk` `RW 0x0`			`l3spclk` `RW 0x0`		`l3mpclk` `RW 0x0`
`dbgdiv` `0x68`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`dbgclk` `RW 0x1`		`dbgatclk` `RW 0x0`
`tracediv` `0x6C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`													`traceclk` `RW 0x0`
`l4src` `0x70`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`l4sp` `RW 0x0`	`l4mp` `RW 0x0`
`stat` `0x74`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`										`outresetack` `RO 0x0`
`Peripheral PLL Group`
`vco` `0x80`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`regextsel` `RW 0x1`	`outreset` `RW 0x0`						`outresetall` `RW 0x0`	`psrc` `RW 0x0`		`denom` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`numer` `RW 0x1`													`pwrdn` `RW 0x1`	`en` `RW 0x0`	`bgpwrdn` `RW 0x1`
`misc` `0x84`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`	`saten` `RW 0x1`	`fasten` `RW 0x0`	`bwadj` `RW 0x1`												`bwadjen` `RW 0x0`
`emac0clk` `0x88`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`cnt` `RW 0x1`
`emac1clk` `0x8C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`cnt` `RW 0x1`
`perqspiclk` `0x90`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`cnt` `RW 0x1`
`pernandsdmmcclk` `0x94`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`cnt` `RW 0x1`
`perbaseclk` `0x98`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`cnt` `RW 0x1`
`s2fuser1clk` `0x9C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`cnt` `RW 0x1`
`en` `0xA0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`				`qspiclk` `RW 0x1`	`nandclk` `RW 0x1`	`nandxclk` `RW 0x1`	`sdmmcclk` `RW 0x1`	`s2fuser1clk` `RW 0x1`	`gpioclk` `RW 0x1`	`can1clk` `RW 0x1`	`can0clk` `RW 0x1`	`spimclk` `RW 0x1`	`usbclk` `RW 0x1`	`emac1clk` `RW 0x1`	`emac0clk` `RW 0x1`
`div` `0xA4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`				`can1clk` `RW 0x0`			`can0clk` `RW 0x0`			`spimclk` `RW 0x0`			`usbclk` `RW 0x0`
`gpiodiv` `0xA8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`								`gpiodbclk` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`gpiodbclk` `RW 0x1`
`src` `0xAC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`										`qspi` `RW 0x1`		`nand` `RW 0x1`		`sdmmc` `RW 0x1`
`stat` `0xB0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`										`outresetack` `RO 0x0`
`SDRAM PLL Group`
`vco` `0xC0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`regextsel` `RW 0x1`	`outreset` `RW 0x0`						`outresetall` `RW 0x0`	`ssrc` `RW 0x0`		`denom` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`numer` `RW 0x1`													`pwrdn` `RW 0x1`	`en` `RW 0x0`	`bgpwrdn` `RW 0x1`
`ctrl` `0xC4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`	`saten` `RW 0x1`	`fasten` `RW 0x0`	`bwadj` `RW 0x1`												`bwadjen` `RW 0x0`
`ddrdqsclk` `0xC8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`											`phase` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`phase` `RW 0x0`							`cnt` `RW 0x1`
`ddr2xdqsclk` `0xCC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`											`phase` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`phase` `RW 0x0`							`cnt` `RW 0x1`
`ddrdqclk` `0xD0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`											`phase` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`phase` `RW 0x0`							`cnt` `RW 0x1`
`s2fuser2clk` `0xD4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`											`phase` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`phase` `RW 0x0`							`cnt` `RW 0x1`
`en` `0xD8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`s2fuser2clk` `RW 0x1`	`ddrdqclk` `RW 0x1`	`ddr2xdqsclk` `RW 0x1`	`ddrdqsclk` `RW 0x1`
`stat` `0xDC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`										`outresetack` `RO 0x0`
`Altera Group`
`alt_mpuclk` `0xE0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`cnt` `RW 0x1`
`alt_mainclk` `0xE4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`cnt` `RW 0x3`
`alt_dbgatclk` `0xE8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`cnt` `RW 0x3`