SDRAM PLL Group Register Descriptions Contains registers with settings for the SDRAM PLL. Offset: 0xc0 vco Contains settings that control the SDRAM PLL VCO. The VCO output frequency is the input frequency multiplied by the numerator (M+1) and divided by the denominator (N+1). Fields are only reset by a cold reset. ctrl Contains VCO control signals and other PLL control signals need to be controllable through register. Fields are only reset by a cold reset. ddrdqsclk Contains settings that control clock ddr_dqs_clk generated from the C0 output of the SDRAM PLL. Fields are only reset by a cold reset. ddr2xdqsclk Contains settings that control clock ddr_2x_dqs_clk generated from the C1 output of the SDRAM PLL. Fields are only reset by a cold reset. ddrdqclk Contains settings that control clock ddr_dq_clk generated from the C2 output of the SDRAM PLL. Fields are only reset by a cold reset. s2fuser2clk Contains settings that control clock s2f_user2_clk generated from the C5 output of the SDRAM PLL. and user documentation refer to s2f_user2_clk as h2f_user2_clk Fields are only reset by a cold reset. en Contains fields that control the SDRAM Clock Group enables generated from the SDRAM PLL clock outputs. 1: The clock is enabled. 0: The clock is disabled. Fields are only reset by a cold reset. stat Contains Output Clock Counter Reset acknowledge status.