s2fuser1clk

Contains settings that control clock s2f_user1_clk generated from the C5 output of the Peripheral PLL. and user documentation refer to s2f_user1_clk as h2f_user1_clk. Only reset by a cold reset.
Module Instance Base Address Register Address
clkmgr 0xFFD04000 0xFFD0409C

Offset: 0x9C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cnt

RW 0x1

s2fuser1clk Fields

Bit Name Description Access Reset
8:0 cnt

Divides the VCO frequency by the value+1 in this field.

RW 0x1