noc_fw_l4_sys_l4_sys_scr Address Map

Module Instance Base Address End Address
noc_fw_l4_sys_l4_sys_scr 0xFFD13100 0xFFD131FF
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Register Offset Width Access Reset Value Description
dma_ecc 0x8 32 RW 0x0 
Per-Master Security bit for dma_ecc
emac0rx_ecc 0xC 32 RW 0x0 
Per-Master Security bit for emac0rx_ecc
emac0tx_ecc 0x10 32 RW 0x0 
Per-Master Security bit for emac0tx_ecc
emac1rx_ecc 0x14 32 RW 0x0 
Per-Master Security bit for emac1rx_ecc
emac1tx_ecc 0x18 32 RW 0x0 
Per-Master Security bit for emac1tx_ecc
emac2rx_ecc 0x1C 32 RW 0x0 
Per-Master Security bit for emac2rx_ecc
emac2tx_ecc 0x20 32 RW 0x0 
Per-Master Security bit for emac2tx_ecc
emac3rx_ecc 0x24 32 RO 0x0 
Per-Master Security bit for emac3rx_ecc
emac3tx_ecc 0x28 32 RO 0x0 
Per-Master Security bit for emac3tx_ecc
nand_ecc 0x2C 32 RW 0x0 
Per-Master Security bit for nand_ecc
nand_read_ecc 0x30 32 RW 0x0 
Per-Master Security bit for nand_read_ecc
nand_write_ecc 0x34 32 RW 0x0 
Per-Master Security bit for nand_write_ecc
onchipram_ecc 0x38 32 RW 0x0 
Per-Master Security bit for onchipram_ecc
qspi_ecc 0x3C 32 RW 0x0 
Per-Master Security bit for qspi_ecc
sdmmc_ecc 0x40 32 RW 0x0 
Per-Master Security bit for sdmmc_ecc
usb0_ecc 0x44 32 RW 0x0 
Per-Master Security bit for usb0_ecc
usb1_ecc 0x48 32 RW 0x0 
Per-Master Security bit for usb1_ecc
clock_manager 0x4C 32 RW 0x0 
Per-Master Security bit for clock_manager
fpga_manager_register 0x50 32 RW 0x0 
Per-Master Security bit for fpga_manager
pin_mux_register 0x54 32 RW 0x0 
Per-Master Security bit for pin_mux_register
reset_manager 0x58 32 RW 0x0 
Per-Master Security bit for reset_manager
system_manager 0x5C 32 RW 0x0 
Per-Master Security bit for system_manager
osc0_timer 0x60 32 RW 0x0 
Per-Master Security bit for osc0_timer
osc1_timer 0x64 32 RW 0x0 
Per-Master Security bit for osc1_timer
watchdog0 0x68 32 RW 0x0 
Per-Master Security bit for watchdog0
watchdog1 0x6C 32 RW 0x0 
Per-Master Security bit for watchdog1
dap 0x70 32 RW 0x0 
Per-Master Security bit for dap
fpga_manager_streaming 0x74 32 RW 0x0 
Per-Master Security bit for fpga_manager_streaming
security_manager_streaming 0x78 32 RW 0x0 
Per-Master Security bit for security_manager_streaming
hmc_register 0x7C 32 RW 0x0 
Per-Master Security bit for hmc_register
hmc_adaptor_register 0x80 32 RW 0x0 
Per-Master Security bit for hmc_adaptor_register
l3_interconnect_register 0x84 32 RW 0x0 
Per-Master Security bit for ddr_scheduler_register
ddr_scheduler_register 0x88 32 RW 0x0 
Per-Master Security bit for ddr_scheduler_register
l4_interconnect_firewall_csr 0x8C 32 RW 0x0 
Per-Master Security bit for noc_firewall_scr
l4_interconnect_probes_csr 0x90 32 RW 0x0 
Per-Master Security bit for noc_probes_register
l4_qos_csr 0x94 32 RW 0x0 
Per-Master Security bit for noc_probes_register